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A front-end circuit for a Monolithic Active Pixel Sensor in 65-nm CMOS Technology

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2024

IEEE Nuclear Science Symposium, DESYTampa, DESY, FL, 26 Oct 2024 - 2 Nov 20242024-10-262024-11-02 [10.1109/NSS/MIC/RTSD57108.2024.10657527]  GO

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Abstract: This work presents an analog front-end circuitry implemented in a monolithic active pixel sensor (MAPS) fabricated in a 65-nm CMOS imaging technology. It combines the low-capacitance collection electrode (< 2 fF) and an analog processor featuring a charge-sensitive amplifier (CSA) driving a fast continuous-time threshold comparator. The CSA features a gain stage along with a Krummenacher-type feedback network. Its gain approximately amounts to 130 µV/e- and provides a rise time of 5 ns. The negative feedback provides leakage current compensation of the sensor diode and a continuous linear discharge of the feedback capacitor. This implements a time-over-threshold (ToT) measurement in combination with the comparator. Threshold voltage and Krummenacher-bias current can be adjusted pixel wise by using a 4-bit and 3-bit DAC, respectively. The prototype shows an input referred noise charge smaller than 35 e-rms. It takes an overall area of 500 µm2, the power consumption is less than 4 µW at a power supply of 1.2 V. Beside design aspects electrical and spectral characterization of a small pixel matrix will be shown in this work.


Contributing Institute(s):
  1. Koordination Elektronik Entwicklung (FE)
Research Program(s):
  1. 622 - Detector Technologies and Systems (POF4-622) (POF4-622)
Experiment(s):
  1. DESY: TestBeamline 21 (DESY II)

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 Record created 2024-11-25, last modified 2025-07-15


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