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| Journal Article | PUBDB-2020-02513 |
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2020
Inst. of Physics
London
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Please use a persistent id in citations: doi:10.1088/1748-0221/15/06/P06023 doi:10.3204/PUBDB-2020-02513
Report No.: arXiv:2004.14116
Abstract: Effects of Single Event Upsets (SEU) and Single Event Transients (SET) are studied in the FE-I4B chip of the innermost layer of the ATLAS pixel system. SEU/SET affect the FE-I4B Global Registers as well as the settings for the individual pixels, causing, among other things, occupancy losses, drops in the low voltage currents, noisy pixels, and silent pixels. Quantitative data analysis and simulations indicate that SET dominate over SEU on the load line of the memory. Operational issues and mitigation techniques are presented.
Keyword(s): semiconductor detector: pixel ; ATLAS ; noise ; electronics: readout ; integrated circuit ; performance ; detector: design ; electronics: design ; signal processing ; numerical calculations
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