Pozniak, K. (Corresponding author)

2005

TESLA Reports 2005 63 pp. (2005) [10.3204/PUBDB-2018-03052]2005  

Report No.: DESY-TESLA-2005-22; TESLA 2005-22

Abstract: The work describes hardware layer of the universal, parameterized communication interfacefor application in the FPGA chips. The interface is called in this work as the „Internal Interface” orin short the “II”. The paper shows how to automatically create the address and data space,according to the user declarations. The methods to standardize the I/O communication withFPGA chips are described. The communication uses library functions and standardized,parametric components in VHDL. Theoretical background and technical description of theInternal Interface are illustrated with a few easy examples of simple interfaces.The name of „Internal Interface” is used by the author and the Warsaw ELHEP ResearchGroup since 2000 for the description of then newly introduced I/O communication standardbetween the user and the FPGA chip. The Internal Interface communication standard has been applied since its first introduction in:• Muon and Energy Trigger for Backing Calorimeter (BAC) in ZEUS experiment (AHDL version) [11],• RPC Muon Trajectory Pattern Comparator Electronics for Compact Muon Solenoid (CMS) inCERN [15],• TESLA Low Level RF Control electronics for TTF II and VUV FEL, as well as for X-RayFEL studies [17-22],• Warsaw ELHEP Laboratory on Electronics for High Energy Physics Experiments for teaching purposes and FPGA electronics development [10] in WUT,• WARSAW CMS Laboratory, for CMS electronics development [14] in the Institute ofExperimental Physics, WU.

Keyword(s): fast logic ; integrated circuit ; programming ; RF system: control system ; free electron laser ; DESY Lab ; FPGA ; FPGA I/O ; VHDL ; Altera ; Xilinx ; communication interface ; behavioral programming ; FPGA systems parameterization and standardization ; FPGA based systems for HEP experiments ; multi-FPGA systems