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| Home > Publications database > Timing Performance of the DESY Chip V2 in a 65 nm CIS Technology |
| Master Thesis | PUBDB-2025-03867 |
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2025
Abstract: Monolithic Active Pixel Sensors (MAPS) produced in CMOS image sensor (CIS) technology are a promising candidate for meeting the stringent requirements for vertex detectors at future lepton colliders. Recently, a 65 nm CIS process has become available to the high-energy physics community, offering enhanced integration density and lowered power consumption. In this context, the DESY Chip V2 was developed as a test chip, studying the performance and intricacies of this technology. The chip features a 2 × 2 pixel test structure with a pixel pitch of 35 × 25 μm2. In contrast to complementary prototypes that rely on reading out digitised data only, the frontend voltage output can be measured, providing deeper insight into the charge collection and frontend response.The work presented in this thesis covers the commissioning and integration of the DESY Chip V2 into existing frameworks, a charge calibration and a test beam campaign with the analysis of the recorded data. Special focus is placed on the time resolution and the interaction of the placement of n-wells with the charge collection.
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