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@ARTICLE{RuizDaza:632796,
      author       = {Ruiz Daza, Sara and Ballabriga, Rafael and Buschmann, Eric
                      and Campbell, Michael and Mohr, Raimon Casanova and
                      Dannheim, Dominik and Dilg, Jona and Dorda, Ana and King,
                      Finn and Feyens, Ono and Gadow, Philipp and Gregor,
                      Ingrid-Maria and Hansen, Karsten and He, Yajun and Huth,
                      Lennart and Kremastiotis, Iraklis and Lemoine, Corentin and
                      Maffessanti, Stefano and Mendes, Larissa and Otarid, Younes
                      and Reckleben, Christian and Rettie, Sébastien and Viera,
                      Manuel Alejandro del Rio and Schlaadt, Judith and Simancas,
                      Adriana and Snoeys, Walter and Spannagel, Simon and Vanat,
                      Tomas and Velyka, Anastasiia and Vignola, Gianpiero and
                      Wennlöf, Håkan},
      title        = {{T}he {H}2{M} {M}onolithic {A}ctive {P}ixel {S}ensor --
                      characterizing non-uniform in-pixel response in a 65 nm
                      {CMOS} imaging technology},
      reportid     = {PUBDB-2025-02221, arXiv:2502.06573},
      year         = {2025},
      abstract     = {The high energy physics community recently gained access to
                      the TPSCo 65 nm ISC (Image Sensor CMOS), which enables a
                      higher in-pixel logic density in monolithic active pixel
                      sensors (MAPS) compared to processes with larger feature
                      sizes. To explore this novel technology, the
                      Hybrid-to-Monolithic (H2M) test chip has been designed and
                      manufactured. The design followed a digital-on-top design
                      workflow and ports a hybrid pixel-detector architecture,
                      with digital pulse processing in each pixel, into a
                      monolithic chip. The chip matrix consists of 64$\times$16
                      square pixels with a size of 35$\times$35 um2, and a total
                      active area of approximately 1.25 um2. The chip has been
                      successfully integrated into the Caribou DAQ system. It is
                      fully functional, and the measured threshold dispersion and
                      noise agree with the expectation from front-end simulations.
                      However, a non-uniform in-pixel response related to the size
                      and location of the n-wells in the analog circuitry has been
                      observed in test beam measurements and will be discussed in
                      this contribution. This asymmetry in the pixel response,
                      enhanced by the 35 um pixel pitch - larger than in other
                      prototypes - and certain features of the readout circuit,
                      has not been observed in prototypes with smaller pixel
                      pitches in this technology.},
      cin          = {ATLAS},
      cid          = {I:(DE-H253)ATLAS-20120731},
      pnm          = {622 - Detector Technologies and Systems (POF4-622) /
                      AIDAinnova - Advancement and Innovation for Detectors at
                      Accelerators (101004761)},
      pid          = {G:(DE-HGF)POF4-622 / G:(EU-Grant)101004761},
      experiment   = {EXP:(DE-H253)LHC-Exp-ATLAS-20150101},
      typ          = {PUB:(DE-HGF)25},
      eprint       = {2502.06573},
      howpublished = {arXiv:2502.06573},
      archivePrefix = {arXiv},
      SLACcitation = {$\%\%CITATION$ = $arXiv:2502.06573;\%\%$},
      doi          = {10.3204/PUBDB-2025-02221},
      url          = {https://bib-pubdb1.desy.de/record/632796},
}