http://join2-wiki.gsi.de/foswiki/pub/Main/Artwork/join2_logo100x88.png
A Practical Introduction to Hardware/Software Codesign
Schaumont, P. R.
2012
Springer
DE
ISBN: 9781461437376
DE : Springer (2012)2012
This record in other databases:
Abstract: This textbook serves as an introduction to the subject of embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which will make the material in this book applicable to a greater number of courses where these tools are already in use. More examples and exercises have been added throughout the book. "If I were teaching a course on this subject, I would use this as a resource and text. If I were a student who wanted to learn codesign, I would look for a course that at least used a similar approach. If I were an engineer or engineering manager who wanted to learn more about codesign from a very practical perspective, I would read this book first before any other. When I first started learning about codesign as a practitioner, a book like this would have been the perfect introduction." --Grant Martin, Tensilica--
Content:
- A Practical Introduction to Hardware/SoftwareCodesign;Preface;Contents;Part I Basic Concepts;Chapter1 The Nature of Hardware and Software;1.1 Introducing Hardware/Software Codesign;1.1.1 Hardware;1.1.2 Software;1.1.3 Hardware and Software;1.1.4 Defining Hardware/Software Codesign;1.2 The Quest for Energy Efficiency;1.2.1 Performance;1.2.2 Energy Efficiency;1.3 The Driving Factors in Hardware/Software Codesign;1.4 The Hardware-Software Codesign Space;1.4.1 The Platform Design Space;1.4.2 Application Mapping;1.5 The Dualism of Hardware Design and Software Design;1.6 Modeling Abstraction Level;1.7 Concurrency and Parallelism;1.8 Summary;1.9 Further Reading;1.10 Problems;Chapter2 Data Flow Modeling and Transformation;2.1 Introducing Data Flow Graphs;2.1.1 Tokens, Actors, and Queues;2.1.2 Firing Rates, Firing Rules, and Schedules;2.1.3 Synchronous Data Flow (SDF) Graphs;2.1.4 SDF Graphs are Determinate;2.2 Analyzing Synchronous Data Flow Graphs;2.2.1 Deriving Periodic Admissible Sequenti
- al Schedules;2.2.2 Example: Deriving a PASS for the PAM-4 System;2.3 Control Flow Modeling and the Limitations of Data FlowModels;2.3.1 Emulating Control Flow with SDF Semantics;2.3.2 Extending SDF Semantics;2.4 Adding Time and Resources;2.4.1 Real-Time Constraints and Input/Output Sample Rate;2.4.2 Data Flow Resource Model;2.4.3 Limits on Throughput;2.5 Transformations;2.5.1 Multirate Expansion;2.5.2 Retiming;2.5.3 Pipelining;2.5.4 Unfolding;2.6 Data Flow Modeling Summary;2.7 Further Reading;2.8 Problems;Chapter3 Data Flow Implementation in Software and Hardware;3.1 Software Implementation of Data Flow;3.1.1 Converting Queues and Actors into Software;3.1.1.1 FIFO Queues;3.1.1.2 Actors;3.1.2 Software Implementation with a Dynamic Scheduler;3.1.3 Example: Four-Point Fast Fourier Transform as an SDF System;3.1.3.1 Multi-thread Dynamic Schedules;3.1.4 Sequential Targets with Static Schedule;3.2 Hardware Implementation of Data Flow;3.2.1 Single-Rate SDF Graphs into Hardware;3.2.2 Pipelinin
- g;3.3 Hardware/Software Implementation of Data Flow;3.4 Summary;3.5 Further Reading;3.6 Problems;Chapter4 Analysis of Control Flow and Data Flow;4.1 Data and Control Edges of a C Program;4.2 Implementing Data and Control Edges;4.3 Construction of the Control Flow Graph;4.4 Construction of the Data Flow Graph;4.5 Application: Translating C to Hardware;4.5.1 Designing the Datapath;4.5.2 Designing the Controller;4.6 Single-Assignment Programs;4.7 Summary;4.8 Further Reading;4.9 Problems;Part II The Design Space of Custom Architectures;Chapter5 Finite State Machine with Datapath;5.1 Cycle-Based Bit-Parallel Hardware;5.1.1 Wires and Registers;5.1.2 Precision and Sign;5.1.3 Hardware Mapping of Expressions;5.2 Hardware Modules;5.3 Finite State Machines;5.4 Finite State Machines with Datapath;5.4.1 Modeling;5.4.2 The FSMD Model As Two Stacked FSM;5.4.3 An FSMD Is Not Unique;5.4.4 Implementation;5.5 FSMD Design Example: A Median Processor;5.5.1 Design Specification: Calculating the Median;5.5.2
- -Mapping the Median in Hardware;5.5.3 Sequentializing the Data Input;5.5.4 Fully Sequentialized Computation;5.6 Proper FSMD;5.7 Language Mapping for FSMD by Example;5.7.1 GCD in GEZEL;5.7.2 GCD in Verilog;5.7.3 GCD in VHDL;5.7.4 GCD in SystemC;5.8 Summary;5.9 Further Reading;5.10 Problems;Chapter6 Microprogrammed Architectures;6.1 Limitations of Finite State Machines;6.1.1 State Explosion;6.1.2 Exception Handling;6.1.3 Runtime Flexibility;6.2 Microprogrammed Control;6.3 Micro-instruction Encoding;6.3.1 Jump Field;6.3.2 Command Field;6.4 The Micro-programmed Datapath;6.4.1 Datapath Architecture;6.4.2 Writing Micro-programs;6.5 Implementing a Micro-programmed Machine;6.5.1 Micro-instruction Word Definition;6.6 Micro-program Interpreters;6.7 Micro-program Pipelining;6.7.1 Micro-instruction Register;6.7.2 Datapath Condition-Code Register;6.7.3 Pipelined Next-Address Logic;6.8 Microprogramming with Microcontrollers;6.8.1 System Architecture;6.8.2 Example: Bresenham Line Drawing;6.9 Summary;
- 6.10 Further Reading;6.11 Problems;Chapter7 General-Purpose Embedded Cores;7.1 Processors;7.1.1 The Toolchain of a Typical Micro-processor;7.1.2 From C to Assembly Instructions;7.2 The RISC Pipeline;7.2.1 Control Hazards;7.2.2 Data Hazards;7.2.3 Structural Hazards;7.3 Program Organization;7.3.1 Data Types;7.3.2 Variables in the Memory Hierarchy;7.3.3 Function Calls;7.3.4 Program Layout;7.4 Compiler Tools;7.4.1 Examining Size;7.4.2 Examining Sections;7.4.3 Examining Assembly Code;7.5 Low-Level Program Analysis;7.6 Processor Simulation;7.6.1 Instruction-Set Simulation;7.6.2 Analysis Based on Execution of Object Code;7.6.3 Simulation at Low Abstraction Level;7.7 Summary;7.8 Further Reading;7.9 Problems;Chapter8 System on Chip;8.1 The System-on-Chip Concept;8.1.1 The Cast of Players;8.1.2 SoC Interfaces for Custom Hardware;8.2 Four Design Principles in SoC Architecture;8.2.1 Heterogeneous and Distributed Data Processing;8.2.2 Heterogeneous and Distributed Communications;8.2.3 Heterogeneous
- -and Distributed Storage;8.2.4 Hierarchical Control;8.3 Example: Portable Multimedia System;8.4 SoC Modeling in GEZEL;8.4.1 An SoC with a StrongARM Core;8.4.2 Ping-Pong Buffer with an 8051;8.4.3 UART on the AVR ATMega128;8.5 Summary;8.6 Further Reading;8.7 Problems;Part III Hardware/Software Interfaces;Chapter9 Principles of Hardware/Software Communication;9.1 Connecting Hardware and Software;9.2 Synchronization Schemes;9.2.1 Synchronization Concepts;9.2.2 Semaphore;9.2.3 One-Way and Two-Way Handshake;9.2.4 Blocking and Non-blocking Data-Transfer;9.3 Communication-Constrained Versus Computation-Constrained;9.4 Tight and Loose Coupling;9.5 Summary;9.6 Further Reading;9.7 Problems;Chapter10 On-Chip Busses;10.1 On-Chip Bus Systems;10.1.1 A Few Existing On-Chip Bus Standards;10.1.2 Elements in a Shared Bus;10.1.3 Elements in a Point-to-Point Bus;10.1.4 Physical Implementation of On-Chip Busses;10.1.5 Bus Naming Convention;10.1.6 Bus Timing Diagram;10.1.7 Definition of the Generic Bus;10.2-
- Bus Transfers;10.2.1 Simple Read and Write Transfers;10.2.2 Transfer Sizing and Endianess;10.2.3 Improved Bus Transfers;10.2.3.1 Transaction Splitting and Pipelined Transfers;10.2.3.2 Burstmode Transfers;10.3 Multi-master Bus Systems;10.3.1 Bus Priority;10.3.2 Bus Locking;10.4 Bus Topologies;10.4.1 Bus Switches;10.4.2 Network On Chip;10.5 Summary;10.6 Further Reading;10.7 Problems;Chapter 11 Microprocessor Interfaces;11.1 Memory-Mapped Interfaces;11.1.1 The Memory-Mapped Register;11.1.2 Mailboxes;11.1.3 First-In First-Out Queues;11.1.4 Slave and Master Handshakes;11.1.5 Shared Memory;11.1.6 GEZEL Modeling of Memory-Mapped Interfaces;11.2 Coprocessor Interfaces;11.2.1 The Fast Simplex Link;11.2.2 The LEON-3 Floating Point Coprocessor Interface;11.3 Custom-Instruction Interfaces;11.3.1 ASIP Design Flow;11.3.2 Example: Endianness Byte-Ordering Processor;11.3.3 Example: The Nios-II Custom-Instruction Interface;11.3.4 Finding Good ASIP Instructions;11.4 Summary;11.5 Further Reading;11.6 Pro
- blems;Chapter12 Hardware Interfaces;12.1 The Coprocessor Hardware Interface;12.1.1 Functions of the Coprocessor Hardware Interface;12.1.2 Layout of the Coprocessor Hardware Interface;12.2 Data Design;12.2.1 Flexible Addressing Mechanisms;12.2.2 Multiplexing and Masking;12.3 Control Design;12.3.1 Hierarchical Control;12.3.2 Control of Internal Pipelining;12.3.2.1 Control of Linear Pipelines;12.3.2.2 Control of Non-linear Pipelines;12.3.2.3 Control Handshakes for Pipelines;12.4 Programmer's Model = Control Design + Data Design;12.4.1 Address Map;12.4.2 Instruction Set;12.5 Summary;12.6 Further Reading;12.7 Problems;Part IV Applications;Chapter13 Trivium Crypto-Coprocessor;13.1 The Trivium Stream Cipher Algorithm;13.1.1 Stream Ciphers;13.1.2 Trivium;13.1.3 Hardware Mapping of Trivium;13.1.4 A Hardware Testbench for Trivium;13.2 Trivium for 8-bit Platforms;13.2.1 Overall Design of the 8051 Coprocessor;13.2.2 Hardware Platform of the 8051 Coprocessor;13.2.3 Software Driver for 8051;13.3 Tri
- vium for 32-bit Platforms;13.3.1 Hardware Platform Using Memory-MappedInterfaces;13.3.2 Software Driver Using Memory-Mapped Interfaces;13.3.3 Hardware Platform Using a Custom-InstructionInterface;13.3.4 Software Driver for a Custom-Instruction Interface;13.4 Summary;13.5 Further Reading;13.6 Problems;Chapter14 AES Co-processor;14.1 AES Encryption and Decryption;14.2 Memory-Mapped AES Encryption Coprocessor;14.2.1 Hardware Interface Operation;14.2.2 Programmer's Model;14.2.3 Software Driver Design;14.2.4 Hardware Interface Design;14.2.5 System Performance Evaluation;14.3 AES Encryption/Decryption with Custom Instructions;14.3.1 AES T-box Reference Implementation;14.3.2 AES T-box Custom Instruction Design;14.3.3 AES T-box Custom Instruction in GEZEL;14.3.4 AES T-box Software Integration and Performance;14.4 Summary;14.5 Further Reading;14.6 Problems;Chapter15 CORDIC Co-processor;15.1 The Coordinate Rotation Digital Computer Algorithm;15.1.1 The Algorithm;15.1.2 Reference Implementation i
- n C;15.2 A Hardware Coprocessor for CORDIC;15.2.1 A CORDIC Kernel in Hardware;15.2.2 A Hardware Interface for Fast-Simplex-Link Coprocessors;15.3 An FPGA Prototype of the CORDIC Coprocessor;15.4 Handling Large Amounts of Rotations;15.5 Summary;15.6 Further Reading;15.7 Problems;AppendixA Hands-on Experiments in GEZEL;A.1 Overview of the GEZEL Tools;A.2 Installing the GEZEL Tools;A.2.1 Installation on a Ubuntu System;A.2.2 Installation of Cross-Compiler Tools;A.2.3 Compiling GEZEL from Source Code on a 32-bitSystem;A.2.3.1 Compiling the Stand-Alone Simulation Tool fdlsim;A.2.3.2 Compiling the Instruction-Set Simulator Simit-ARM;A.2.3.3 Compiling the Instruction-Set Simulator simulavr;A.2.3.4 Compiling the Cosimulation Tool gplatform;A.2.3.5 Compiling the Code Generation Tool fdlvhd;A.2.4 Compiling GEZEL from Source Code on a 64-bitSystem;A.2.4.1 Compiling the Instruction-Set Simulator Simitarm (on 64-bit Platform);A.2.4.2 Compiling the Cosimulation Tool gplatform (on 64-bit Platfo..
guest ::
