Home > Publications database > Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70$~\mu$m pixel pitch > print |
001 | 598042 | ||
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024 | 7 | _ | |a 10.1088/1748-0221/19/01/P01020 |2 doi |
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024 | 7 | _ | |a arXiv:2311.13220 |2 arXiv |
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100 | 1 | _ | |a Diehl, Inge |0 P:(DE-H253)PIP1000066 |b 0 |e Corresponding author |u desy |
245 | _ | _ | |a Monolithic MHz-frame rate digital SiPM-IC with sub-100 ps precision and 70$~\mu$m pixel pitch |
260 | _ | _ | |a London |c 2024 |b Inst. of Physics |
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500 | _ | _ | |a 16 pages, 13 figures, 1 table |
520 | _ | _ | |a This paper presents the design and characterization of a monolithic integrated circuit (IC) including digital silicon photomultipliers (dSiPMs) arranged in a 32$~\times~$32 pixel matrix at 70$~\mu$m pitch. The IC provides per-quadrant time stamping and hit-map readout, and is fabricated in a standard 150-nm CMOS technology. Each dSiPM pixel consists of four single-photon avalanche diodes (SPADs) sharing a quenching and subsequent processing circuitry and has a fill factor of 30$~\%$. A sub-100$~$ps precision, 12-bit time-to-digital converter (TDC) provides timestamps per quadrant with an acquisition rate of 3$~$MHz. Together with the hit map, the total sustained data throughput of the IC amounts to 4$~$Gbps. Measurements obtained in a dark, temperature-stable environment as well as by using a pulsed laser environment show the full dSiPM-IC functionality. The dark-count rate (DCR) as function of the overvoltage and temperature, the TDC resolution, differential and integral nonlinearity (DNL/INL) as well as the propagation-delay variations across the matrix are presented. With aid of additional peripheral test structures, the main building blocks are characterized and key parameters are presented. |
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542 | _ | _ | |i 2024-01-18 |2 Crossref |u http://creativecommons.org/licenses/by/4.0/ |
542 | _ | _ | |i 2024-01-18 |2 Crossref |u https://iopscience.iop.org/info/page/text-and-data-mining |
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