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@INPROCEEDINGS{Boebel:486085,
      author       = {Boebel, Artur and Ceslik, Harald and Dam, M. and Diez
                      Cornell, Sergio and Garvey, Cameron Michael and Göttlicher,
                      Peter and Gregor, Ingrid-Maria and Keaveney, James Michael
                      and Merwe, Max Nikoi van der and Oechsle, J. and Schmitt,
                      Stefan and Stanitzki, Marcel and Stroem, Lars Rickard and
                      Wyngaard, J. R.},
      title        = {{C}urrent status of the {E}nd-of-{S}ubstructure ({E}o{S})
                      card project for the {ATLAS} {S}trip {T}racker using final
                      {ASIC}s},
      reportid     = {PUBDB-2022-07081},
      year         = {2022},
      abstract     = {The silicon tracker of the ATLAS experiment will be
                      upgraded for the upcoming High-Luminosity Upgradeof the LHC
                      (HL-LHC). The main building blocks of the new strip tracker
                      are modules that consist ofsilicon sensors and hybrid PCBs
                      hosting the read-out ASICs. The modules are mounted on rigid
                      carbon fibresubstructures, known as staves in the central
                      barrel region and petals in the end-cap regions, thatprovide
                      common services to all the modules. At the end of each stave
                      or petal side, a so-called End-of-Substructure (EoS) card
                      facilitates the transfer of data, power, and control signals
                      between the modulesand the off-detector systems. The module
                      front-end electronics transfer data to the EoS card on
                      640Mbit/s differential lines. The EoS connects up to 28 data
                      lines to one or two lpGBT chips that providedata
                      serialisation and uses a 10 GBit/s versatile optical link
                      (VTRx+) to transmit signals to the off-detectorsystems. The
                      lpGBT also recovers the LHC clock on the downlink and
                      generates clock and control signalsfor the modules. To meet
                      the tight integration requirements in the detector, several
                      different EoScard designs are needed. Custom-made holders
                      and clamps are produced to guide cables and opticalfibres as
                      well as to shield the sensors from the opto-electric system.
                      Here we present the production readyEoS card’s electronic
                      design integrating final lpGBTv1 and VTRx+ ASICs from CERN,
                      as well asresults from recent quality assurance tests
                      including detailed characterisation of the
                      opto-electronicssystem by its bit error rate, jitter, and
                      eye diagram representation. Since each EoS sits at a
                      single-point-of-failure for an entire stave or petal side, a
                      dedicated quality control (QC) procedure for the production
                      has been developed. An overview of the QC will also be
                      presented.},
      month         = {Sep},
      date          = {2022-09-19},
      organization  = {Topical Workshop of Electronics for
                       Particle Physics, Bergen (Norway), 19
                       Sep 2022 - 23 Sep 2022},
      cin          = {FE / FEB / FEA / FTX / ATLAS},
      cid          = {I:(DE-H253)FE-20120731 / I:(DE-H253)FEB-20120731 /
                      I:(DE-H253)FEA-20120731 / I:(DE-H253)FTX-20210408 /
                      I:(DE-H253)ATLAS-20120731},
      pnm          = {611 - Fundamental Particles and Forces (POF4-611)},
      pid          = {G:(DE-HGF)POF4-611},
      experiment   = {EXP:(DE-H253)LHC-Exp-ATLAS-20150101},
      typ          = {PUB:(DE-HGF)6},
      url          = {https://bib-pubdb1.desy.de/record/486085},
}