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@ARTICLE{Khilo:144108,
author = {Khilo, A. and Spector, S. J. and Grein, M. E. and
Nejadmalayeri, A. H. and Holzwarth, C. W. and Sander, M. Y.
and Dahlem, M. S. and Peng, M. Y. and Geis, M. W. and
Dilello, N. A. and Yoon, J. U. and Motamedi, A. and Orcutt,
J. S. and Wang, J. P. and Sorace-Agaskar, C. M. and
$Popovi\'c,$ M. A. and Sun, J. and Zhou, G.-R. and Byun, H.
and Chen, J. and Hoyt, J. L. and Smith, H. I. and Ram, R. J.
and Perrott, M. and Lyszczarz, T. M. and Ippen, E. P. and
Kärtner, F. X. and DESY},
title = {{P}hotonic {ADC}: overcoming the bottleneck of electronic
jitter},
journal = {Optics express},
volume = {20},
issn = {1094-4087},
address = {Washington, DC},
publisher = {Soc.},
reportid = {PHPPUBDB-25804},
pages = {4454},
year = {2012},
abstract = {Accurate conversion of wideband multi-GHz analog signals
into the digital domain has long been a target of
analog-to-digital converter (ADC) developers, driven by
applications in radar systems, software radio, medical
imaging, and communication systems. Aperture jitter has been
a major bottleneck on the way towards higher speeds and
better accuracy. Photonic ADCs, which perform sampling using
ultra-stable optical pulse trains generated by mode-locked
lasers, have been investigated for many years as a promising
approach to overcome the jitter problem and bring ADC
performance to new levels. This work demonstrates that the
photonic approach can deliver on its promise by digitizing a
41 GHz signal with 7.0 effective bits using a photonic ADC
built from discrete components. This accuracy corresponds to
a timing jitter of 15 fs - a 4-5 times improvement over the
performance of the best electronic ADCs which exist today.
On the way towards an integrated photonic ADC, a silicon
photonic chip with core photonic components was fabricated
and used to digitize a 10 GHz signal with 3.5 effective
bits. In these experiments, two wavelength channels were
implemented, providing the overall sampling rate of 2.1
GSa/s. To show that photonic ADCs with larger channel counts
are possible, a dual 20-channel silicon filter bank has been
demonstrated.},
cin = {FS-CFEL-2},
ddc = {530},
cid = {I:(DE-H253)FS-CFEL-2-20120731},
pnm = {Experiments at CFEL (POF2-544)},
pid = {G:(DE-H253)POF2-CFEL-Exp.-20130405},
experiment = {EXP:(DE-H253)CFEL-Exp-20150101},
typ = {PUB:(DE-HGF)16},
pubmed = {pmid:22418205},
UT = {WOS:000301041900111},
doi = {10.1364/OE.20.004454},
url = {https://bib-pubdb1.desy.de/record/144108},
}